1. Field of the Invention
The present invention relates to a method for manufacturing capacitor lower electrodes of a semiconductor memory, and more particularly to a method for manufacturing capacitor lower electrodes of a stack dynamic random access memory.
2. Description of Related Art
Dynamic random access memory is one kind of semiconductor memory. Each memory cell of a dynamic random access memory is composed of a field effect transistor and a capacitor, and a source or a drain of the field effect transistor is electrically connected with the capacitor. Capacitors can be categorized into stacked type capacitors and deep trench type capacitors, wherein the stacked type capacitors are directly formed over surfaces of semiconductor substrates containing field effect transistors and the deep trench type capacitors are formed in semiconductor substrates.
As shown in FIGS. 1-5, a conventional method for manufacturing capacitor lower electrodes of a semiconductor memory is provided. At first, the method includes fabricating a semiconductor substrate 1a which has a field effect transistor (not shown) and a plurality of conductive plugs 11a electrically connected with a source or a drain of the field effect transistor; secondly, forming a stacked structure 2a on an upper surface of the semiconductor substrate 1a, wherein the stacked structure 2a includes an insulating oxide layer 21a, a dielectric layer 22a and an insulating nitride layer 3a from bottom to top, and the insulating oxide layer 21a, the dielectric layer 22a and the insulating nitride layer 23a have different etching rates for acid. As shown in FIG. 2, after the stacked structure 2a is formed, adopting a yellow light technology to form a plurality of trenches 24a, so that the conductive plugs 11a are exposed in the trenches 24a. Then, forming a conductive metal material 25a and a capacitor lower electrode 26a of which the cross-section is in a U shape in each trench 24a. Thus, the conductive metal material 25a is contacted with the conductive plugs 11a and the capacitor lower electrodes 26a is located on the conductive metal material 25a. Then, the insulating nitride layer 23a and the capacitor lower electrodes 26a (as shown in FIG. 1 and FIG. 3, the step is called as Lattice etch) are partially etched to form an elliptic etching-area, and the dielectric layer 22a is etched and removed from the etching-area (as shown in FIG. 4).
To improve data storage capacity of memories, density of memory cells must be increased. The solution for solving the problem is to decrease dimensions in a semiconductor fabrication process or increase surface areas of the capacitor lower electrodes 26a. However, when dimensions are getting smaller, the semiconductor fabrication processing of the U-shaped capacitor lower electrodes 26a is getting more difficult. Whether the dimensions become smaller or the surface areas are increased causes that the supporting stress becomes lower. Consequently, it is very difficult to fabricate the dielectric layer and capacitor upper electrodes outside the capacitor lower electrodes 26a for preventing from collapsing or producing deformation.
Hence, the inventors of the present invention believe that the shortcomings described above are able to be improved and finally suggest the present invention which is of a reasonable design and is an effective improvement based on deep research and thought.